Portable information terminals such as portable telephones and laptop computers use rechargeable batteries as their power source. When these battery-powered terminals are continuously used, however, their maximum operation time will be a few hours at most. Therefore, to extend the operation time of these terminals, it is essential to improve their power-saving function to efficiently use the battery power. One known power-saving function shifts to a power-saving mode by stopping supply of clocks to the processor or reducing the frequency level of the clocks during idle time, that is, when there exists no task to be executed by the processor, in order to reduce the power consumed by the processor. The processor which has been shifted to the power-saving mode is restarted using a timer interrupt from a hardware timer as a trigger.
FIG. 1 is a conceptual diagram showing a conventional processor power-saving control method. In FIG. 1, reference numeral 22 denotes a processor. Reference numeral 23 denotes a first OS; 24 a hardware timer for issuing a timer interrupt to the first OS 23 at predetermined time intervals (periodic interrupt) or at a specified time (non-periodic interrupt); 25 a timer handler for receiving a timer interrupt from the hardware timer 24; 26 a scheduler called by the timer handler 25 for executing tasks in an orderly manner; 27 a power-saving mechanism which is called by the scheduler 26 when there is no task to be executed and which shifts the processor 22 to the power-saving mode; and 28 a task to be executed by the first OS 23. The hardware timer 24 issues a timer interrupt to the first OS 23 and outputs a start-up signal to the processor 22 in the power-saving mode to restart it, at the same time.
On the other hand, reference numeral 29 denotes a second OS; 30 a hardware timer for issuing a timer interrupt to the second OS 29 at predetermined time intervals (periodic interrupt) or at a specified time (non-periodic interrupt); 31 a timer handler for receiving a timer interrupt from the hardware timer 30; 32 a scheduler called by the timer handler 31 for executing tasks in an orderly manner; 33 a power-saving mechanism which is called by the scheduler 32 when there is no task to be executed and which shifts the processor 22 to the power-saving mode; and 34 a task to be executed by the second OS. The hardware timer 30 issues a timer interrupt to the second OS 29 and outputs a start-up signal to the processor 22 in the power-saving mode to restart it, at the same time.
As described above, the hardware timers 24 and 30 are provided for the first OS 23 and the second OS 29, respectively. That is, the hardware timers 24 and 30 issue timer interrupts to the first OS 23 and the second OS 29, separately and respectively. Accordingly, in the conventional processor power-saving control method, the processor 22 is restarted each time a timer interrupt is issued to an OS, which makes it difficult to efficiently keep the power-saving mode.
To solve the above problem, an object of the present invention is to propose a processor power-saving control method and a processor power-saving control device executing the method employed in the environment in which a plurality of OSs exist on a single processor, wherein the processor power-saving control method can collectively control a timer interrupt issued to each OS so as to reduce the number of timer interrupts to be issued, efficiently maintaining the processor power-saving mode.